HD64F38024HV Datasheet, PDF (186/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 6 ROM
6.6.3 Erase Block Register (EBR)
Bit
7
6
5
—
—
—
Initial value
0
0
0
Read/Write
—
—
—
4
3
2
1
0
EB4
EB3
EB2
EB1
EB0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in
FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be
automatically cleared to 0. When each bit is set to 1 in EBR, the corresponding block can be
erased. Other blocks change to the erase-protection state. See table 6.6 for the method of dividing
blocks of the flash memory. When the whole bits are to be erased, erase them in turn in unit of a
block.
Table 6.6 Division of Blocks to Be Erased
EBR
0
1
2
3
4
Bit Name
EB0
EB1
EB2
EB3
EB4
Block (Size)
EB0 (1 Kbyte)
EB1 (1 Kbyte)
EB2 (1 Kbyte)
EB3 (1 Kbyte)
EB4 (12 Kbytes)
EB4 (28 Kbytes)
Address
H'0000 to H'03FF
H'0400 to H'07FF
H'0800 to H'0BFF
H'0C00 to H'0FFF
H'1000 to H'3FFF (HD64F38122)
H'1000 to H'7FFF (HD64F38124,
HD64F38024, HD64F38024R)
6.6.4 Flash Memory Power Control Register (FLPWCR)
Bit
7
6
5
4
3
2
1
0
PDWND —
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
—
—
—
—
—
—
—
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. The power supply circuit can be read in the subactive mode, although
it is partly halted in the power-down mode.
Rev. 8.00 Mar. 09, 2010 Page 164 of 658
REJ09B0042-0800