HD64F38024HV Datasheet, PDF (331/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Bit 3
CKS3
1
Bit 2
CKS2
0
Bit 1
CKS1
0
1
1
0
1
0
X
X
Note: X: Don't care
Bit 0
CKS0
0
1
0
1
0
1
0
1
X
Description
Internal clock: φ/64 count
Internal clock: φ/128 count
Internal clock: φ/256 count
Internal clock: φ/512 count
Internal clock: φ/1024 count
Internal clock: φ/2048 count
Internal clock: φ/4096 count
Internal clock: φ/8192 count
Watchdog on-chip oscillator
Section 9 Timers
(initial value)
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
LVDCKSTD^* ⎯
Initial value
1
1
Read/Write R/W
⎯
5
4
3
2
1
0
⎯ PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP
1
1
1
1
1
1
⎯
R/W
R/W
R/W
R/W
R/W
Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group.
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the watchdog timer is described here. For details of the other
bits, see the sections on the relevant modules.
Bit 2—Watchdog Timer Module Standby Mode Control (WDCKSTP)
Bit 2 controls setting and clearing of module standby mode for the watchdog timer.
WDCKSTP Description
0
Watchdog timer is set to module standby mode
1
Watchdog timer module standby mode is cleared
(initial value)
Note:
WDCKSTP is valid when the WDON bit is cleared to 0 in timer control/status register W
(TCSRW). If WDCKSTP is set to 0 while WDON is set to 1 (during watchdog timer
operation), 0 will be set in WDCKSTP but the watchdog timer will continue its watchdog
function and will not enter module standby mode. When the watchdog function ends and
WDON is cleared to 0 by software, the WDCKSTP setting will become valid and the
watchdog timer will enter module standby mode.
Rev. 8.00 Mar. 09, 2010 Page 309 of 658
REJ09B0042-0800