HD64F38024HV Datasheet, PDF (376/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 10 Serial Communication Interface
Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2)
φ
Bit Rate
(bit/s)
n
5 MHz
N
Error n
8 MHz
N
Error n
200
—
—
—
—
—
—
0
250
—
—
—
3
124
0
2
300
—
—
—
—
—
—
0
500
—
—
—
2
249 0
0
1K
—
—
—
2
124 0
0
2.5K
—
—
—
2
49
0
0
5K
0
249 0
2
24
0
0
10K
0
124 0
0
199
0
0
25K
0
49
0
0
79
0
0
50K
0
24
0
0
39
0
0
100K
—
—
—
0
19
0
0
250K
0
4
0
0
7
0
0
500K
—
—
—
0
3
0
0
1M
—
—
—
0
1
0
—
Blank: Cannot be set.
— : A setting can be made, but an error will result.
10 MHz
N
Error
12499 0
624 0
8332 0
4999 0
2499 0
999 0
499 0
249 0
99
0
49
0
24
0
9
0
4
0
—
—
Notes: The value set in BRR is given by the following equation:
φ
N = _{(4 × 22n × B)} – 1
where
B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
φ: System clock frequency
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.7.)
Rev. 8.00 Mar. 09, 2010 Page 354 of 658
REJ09B0042-0800