HD64F38024HV Datasheet, PDF (104/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 3 Exception Handling
Bit 2—IRQAEC Interrupt Enable (IENEC2)
Bit 2 enables or disables IRQAEC interrupt requests.
Bit 2
IENEC2
0
1
Description
Disables IRQAEC interrupt requests
Enables IRQAEC interrupt requests
(initial value)
Bits 1 and 0—IRQ₁ and IRQ₀ Interrupt Enable (IEN1 and IEN0)
Bits 1 and 0 enable or disable IRQ₁ and IRQ₀ interrupt requests.
Bit n
IENn
0
1
Description
Disables interrupt requests from pin IRQn
Enables interrupt requests from pin IRQn
(initial value)
(n = 1 or 0)
Interrupt Enable Register 2 (IENR2)
Bit
7
6
5
4
3
2
1
0
IENDT IENAD — IENTG IENTFH IENTFL IENTC IENEC
Initial value
0
0
—
0
0
0
0
0
Read/Write
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Direct Transfer Interrupt Enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT
0
1
Description
Disables direct transfer interrupt requests
Enables direct transfer interrupt requests
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 82 of 658
REJ09B0042-0800