HD64F38024HV Datasheet, PDF (105/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Bit 6—A/D Converter Interrupt Enable (IENAD)
Bit 6 enables or disables A/D converter interrupt requests.
Bit 6
IENAD
0
1
Description
Disables A/D converter interrupt requests
Enables A/D converter interrupt requests
Section 3 Exception Handling
(initial value)
Bit 5—Reserved
Bit 5 is reserved bit: it can only be written with 0.
Bit 4—Timer G Interrupt Enable (IENTG)
Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Bit 4
IENTG
0
1
Description
Disables timer G interrupt requests
Enables timer G interrupt requests
(initial value)
Bit 3—Timer FH Interrupt Enable (IENTFH)
Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3
IENTFH
0
1
Description
Disables timer FH interrupt requests
Enables timer FH interrupt requests
(initial value)
Bit 2—Timer FL Interrupt Enable (IENTFL)
Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2
IENTFL
0
1
Description
Disables timer FL interrupt requests
Enables timer FL interrupt requests
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 83 of 658
REJ09B0042-0800