HD64F38024HV Datasheet, PDF (80/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 2 CPU
CPU state
Reset state
The CPU is initialized
Program
execution state
Program halt state
A state in which some
or all of the chip
functions are stopped
to conserve power
Active
(high speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Active
(medium speed) mode
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
Subactive mode
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock
Sleep (high-speed)
mode
Low-power
modes
Sleep (medium-speed)
mode
Standby mode
Watch mode
Subsleep mode
Exception-
handling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Note: See section 5, Power-Down Modes, for details on the modes and their transitions.
Figure 2.14 CPU Operation States
Rev. 8.00 Mar. 09, 2010 Page 58 of 658
REJ09B0042-0800