HD64F38024HV Datasheet, PDF (101/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 3 Exception Handling
3.3.2 Interrupt Control Registers
Table 3.3 lists the registers that control interrupts.
Table 3.3 Interrupt Control Registers
Name
Abbreviation R/W
IRQ edge select register
IEGR
R/W
Interrupt enable register 1
IENR1
R/W
Interrupt enable register 2
Interrupt request register 1
Interrupt request register 2
Wakeup interrupt request register
IENR2
IRR1
IRR2
IWPR
R/W
R/W^*
R/W^*
R/W^*
Wakeup edge select register
WEGR
R/W
Note: * Write is enabled only for writing of 0 to clear a flag.
Initial Value
—
—
—
—
—
H'00
H'00
Address
H'FFF2
H'FFF3
H'FFF4
H'FFF6
H'FFF7
H'FFF9
H'FF90
IRQ Edge Select Register (IEGR)
Bit
7
⎯
Initial value
1
Read/Write
⎯
6
5
4
3
2
1
0
⎯
⎯
IEG4 IEG3
⎯
IEG1 IEG0
1
1
0
0
⎯
0
0
⎯
⎯
R/W R/W
W
R/W R/W
IEGR is an 8-bit read/write register used to designate whether pins IRQ₄, IRQ₃, IRQ_1, and IRQ₀
are set to rising edge sensing or falling edge sensing. For the IRQAEC pin edge sensing
specifications, see section 9.7, Asynchronous Event Counter (AEC).
Bits 7 to 5—Reserved
Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 79 of 658
REJ09B0042-0800