HD64F38024HV Datasheet, PDF (372/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 10 Serial Communication Interface
10.2.8 Bit Rate Register (BRR)
Bit
Initial value
Read/Write
7
BRR7
1
R/W
6
BRR6
1
R/W
5
BRR5
1
R/W
4
BRR4
1
R/W
3
BRR3
1
R/W
2
BRR2
1
R/W
1
BRR1
1
R/W
0
BRR0
1
R/W
BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR).
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
Table 10.3 shows examples of BRR settings in asynchronous mode. The values shown are for
active (high-speed) mode.
Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Bit Rate
(bit/s)
110
150
200
250
300
600
1200
2400
4800
9600
19200
31250
38400
φ
16.4 kHz
19.2 kHz
1 MHz
1.2288 MHz
Error
Error
Error
Error
n N (%) n N (%) n N (%) n N (%) n
— — — — — — 2 17 –1.36 2 21 –0.83 3
— — — 0 3 0 2 12 0.16 3 3 0 2
— — — 0 2 0 2 9 –2.34 3 2 0 3
0 1 2.5 — — — 3 1 –2.34 0 153 –0.26 2
— — — 0 1 0 0 103 0.16 3 1 0 2
— — — 0 0 0 0 51 0.16 3 0 0 0
— — — 0 25 0.16 2 1 0 0
— — — 0 12 0.16 2 0 0 0
——— ——— 0 7 0 0
——— ——— 0 3 0 —
——— ——— 0 1 0 —
——— 0 0 0 ——— 0
——— ——— 0 0 0 —
2 MHz
Error
N (%)
8 –1.36
25 0.16
4 –2.34
15 –2.34
12 0.16
103 0.16
51 0.16
25 0.16
12 0.16
——
——
10
——
Rev. 8.00 Mar. 09, 2010 Page 350 of 658
REJ09B0042-0800