HD64F38024HV Datasheet, PDF (373/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 10 Serial Communication Interface
Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
φ
5 MHz
8 MHz
10 MHz
Bit Rate
Error
Error
Error
(bit/s) n N (%) n N (%) n N (%)
110
3 21 0.88 3 35 –1.36 3 43 0.88
150
3 15 1.73 3 25 0.16 3 32 –1.36
200
3 11 1.73 3 19 –2.34 3 23 1.73
250
3 9 –2.34 3 15 –2.34 3 19 –2.34
300
3 7 1.73 3 12 0.16 3 15 1.73
600
3 3 1.73 2 25 0.16 3 7 1.73
1200
3 1 1.73 2 12 0.16 3 3 1.73
2400
3 0 1.73 0 103 0.16 3 1 1.73
4800
2 1 1.73 0 51 0.16 3 0 1.73
9600
2 0 173 0 25 0.16 2 1 1.73
19200 0 7 1.73 0 12 0.16 2 0 1.73
31250 0 4 0 0 7 0 0 9 0
38400 0 3 1.73 — — — 0 7 1.73
Notes: No indication: Setting not possible.
—: Setting possible, but errors may result.
1. The value set in BRR is given by the following equation:
φ
N = _{(32 × 22n × B)} – 1
where
B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
φ: System clock frequency
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.4.)
2. The error in table 10.3 is the value obtained from the following equation, rounded to two
decimal places.
B (rate obtained from n, N, OSC) – R(bit rate in left-hand column in table 10.3.)
Error (%) =
× 100
R (bit rate in left-hand column in table 10.3.)
Rev. 8.00 Mar. 09, 2010 Page 351 of 658
REJ09B0042-0800