HD64F38024HV Datasheet, PDF (291/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 9 Timers
Bit 3—Toggle Output Level L (TOLL)
Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is
written.
Bit 3
TOLL
0
1
Description
Low level
High level
(initial value)
Bits 2 to 0—Clock Select L (CKSL2 to CKSL0)
Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external
event input.
Bit 2
Bit 1
Bit 0
CKSL2 CKSL1 CKSL0 Description
0
0
0
Counting on external event (TMIF) rising/falling edge^*
0
0
1
(initial value)
0
1
0
0
1
1
Use prohibited
1
0
0
Internal clock: counting on φ/32
1
0
1
Internal clock: counting on φ/16
1
1
0
Internal clock: counting on φ/4
1
1
1
Internal clock: counting on φw/4
Note: * External event edge selection is set by IEG3 in the IRQ edge select register (IEGR). For
details, see IRQ Edge Select Register (IEGR) in section 3.3.2, Interrupt Control Registers.
Note that the timer F counter may increment if the setting of IRQ3 in port mode register 1
(PMR1) is changed from 0 to 1 or from 1 to 0 while the TMIF pin is low in order to change
the TMIF pin function.
Rev. 8.00 Mar. 09, 2010 Page 269 of 658
REJ09B0042-0800