HD64F38024HV Datasheet, PDF (421/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 12 A/D Converter
Bit 7—Clock Select (CKS)
Bit 7 sets the A/D conversion speed.
Bit 7
CKS
Conversion Period
φ = 1 MHz
Conversion Time
φ = 5 MHz
φ = 10 MHz^*2
0
62/φ (initial value)
1
31/φ
62 µs
31 µs
12.4 µs
—^*1
6.2 µs
—^*1
Notes: 1. With the H8/38024, H8/38024S, and H8/38024F-ZTAT operation cannot be guaranteed
if the conversion time is less than 12.4 µs. Make sure to select a setting that gives a
conversion time of 12.4 µs or more.
With the H8/38124 Group operation cannot be guaranteed if the conversion time is less
than 6.2 μs. Make sure to select a setting that gives a conversion time of 6.2 μs or
more.
2. H8/38124 Group only.
Bit 6—External Trigger Select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE
Description
0
Disables start of A/D conversion by external trigger
(initial value)
1
Enables start of A/D conversion by rising or falling edge of external trigger at pin
ADTRG^*
Note: * The external trigger (ADTRG) edge is selected by bit IEG4 of IEGR. See 1. IRQ edge
select register (IEGR) in section 3.3.2, Interrupt Control Registers, for details.
Bits 5 and 4—Reserved
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 399 of 658
REJ09B0042-0800