HD64F38024HV Datasheet, PDF (183/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 6 ROM
Bit 6—Software Write Enable (SWE)
This bit is to set enabling/disabling of programming/enabling of flash memory (set when bits 5 to
0 and the EBR register are to be set).
Bit 6
SWE
0
1
Description
Programming/erasing is disabled. Other FLMCR1 register bits and all EBR bits
cannot be set.
(initial value)
Flash memory programming/erasing is enabled.
Bit 5—Erase Setup (ESU)
This bit is to prepare for changing to erase mode. Set this bit to 1 before setting the E bit to 1 in
FLMCR1 (do not set SWE, PSU, EV, PV, E, and P bits at the same time).
Bit 5
ESU
0
1
Description
The erase setup state is cancelled
(initial value)
The flash memory changes to the erase setup state. Set this bit to 1 before setting
the E bit to 1 in FLMCR1.
Bit 4—Program Setup (PSU)
This bit is to prepare for changing to program mode. Set this bit to 1 before setting the P bit to 1
in FLMCR1 (do not set SWE, ESU, EV, PV, E, and P bits at the same time).
Bit 4
PSU
0
1
Description
The program setup state is cancelled
(initial value)
The flash memory changes to the program setup state. Set this bit to 1 before
setting the P bit to 1 in FLMCR1.
Bit 3—Erase-Verify (EV)
This bit is to set changing to or cancelling erase-verify mode (do not set SWE, ESU, PSU, PV, E,
and P bits at the same time).
Rev. 8.00 Mar. 09, 2010 Page 161 of 658
REJ09B0042-0800