HD64F38024HV Datasheet, PDF (566/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Appendix A CPU Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Fetch
Addr. Read Operation
I
J
K
Byte Data
Access
L
Word Data Internal
Access
Operation
M
N
BTST
BTST Rn, @aa:8
2
1
BXOR
BXOR #xx:3, Rd
1
BXOR #xx:3, @Rd
2
1
BXOR #xx:3, @aa:8
2
1
CMP
CMP. B #xx:8, Rd
1
CMP. B Rs, Rd
1
CMP.W Rs, Rd
1
DAA
DAA.B Rd
1
DAS
DAS.B Rd
1
DEC
DEC.B Rd
1
DIVXU
DIVXU.B Rs, Rd
1
EEPMOV EEPMOV
2
12
2n+2^*
1^*
INC
INC.B Rd
1
JMP
JMP @Rn
2
JMP @aa:16
2
2
JMP @@aa:8
2
1
2
JSR
JSR @Rn
2
1
JSR @aa:16
2
1
2
JSR @@aa:8
2
1
1
LDC
LDC #xx:8, CCR
1
LDC Rs, CCR
1
MOV
MOV.B #xx:8, Rd
1
MOV.B Rs, Rd
1
MOV.B @Rs, Rd
1
1
MOV.B @(d:16, Rs), Rd 2
1
MOV.B @Rs+, Rd
1
1
2
MOV.B @aa:8, Rd
1
1
MOV.B @aa:16, Rd
2
1
MOV.B Rs, @Rd
1
1
MOV.B Rs, @(d:16, Rd) 2
1
MOV.B Rs, @–Rd
1
1
2
MOV.B Rs, @aa:8
1
1
MOV.B Rs, @aa:16
2
1
MOV.W #xx:16, Rd
2
MOV.W Rs, Rd
1
MOV.W @Rs, Rd
1
1
MOV.W @(d:16, Rs), Rd 2
1
MOV.W @Rs+, Rd
1
1
2
MOV.W @aa:16, Rd
2
1
Note: * n: Initial value in R4L. The source and destination operands are accessed n + 1 times each.
Internal operation N is 0 for HD64F38024, HD64F38024F, H8/38024S Group and H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 544 of 658
REJ09B0042-0800