HD64F38024HV Datasheet, PDF (628/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Appendix B Internal I/O Registers
IRR1—Interrupt Request Register 1
Bit
7
6
5
IRRTA ⎯
⎯
Initial value
0
⎯
1
Read/Write R/(W)^* W
⎯
H'F6
System Control
4
IRRI4
0
R/(W)^*
3
2
IRRI3 IRREC2
0
0
R/(W)^* R/(W)^*
1
IRRI1
0
R/(W)^*
0
IRRI0
0
R/(W)^*
IRQ1 and IRQ0 Interrupt Request Flags
0 Clearing condition:
When IRRIn = 1, it is cleared by writing 0
1 Setting condition:
When pin IRQn is designated for interrupt
input and the designated signal edge is input
IRQAEC Interrupt Request Flag
(n = 1 or 0)
0 Clearing condition:
When IRREC2 = 1, it is cleared by writing 0
1 Setting condition:
When pin IRQAEC is designated for interrupt
input and the designated signal edge is input
IRQ4 and IRQ3 Interrupt Request Flags
0 Clearing condition:
When IRRIm = 1, it is cleared by writting 0
1 Setting condition:
When pin IRQm is designated for interrupt
input and the designated signal edge is input
Timer A Interrupt Request Flag
(m = 4 or 3)
0 Clearing condition:
When IRRTA = 1, it is cleared by writing 0
1 Setting condition:
When the timer A counter value overflows (from H'FF to H'00)
Note: * Bits 7 and 4 to 0 can only be written with 0, for flag clearing.
Rev. 8.00 Mar. 09, 2010 Page 606 of 658
REJ09B0042-0800