HD64F38024HV Datasheet, PDF (623/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

SYSCR2—System Control Register 2
Appendix B Internal I/O Registers
H'F1
System Control
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯ NESEL DTON MSON SA1 SA0
Initial value
1
1
1
1
0
0
0
0
Read/Write
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
Subactive Mode Clock Select
Medium Speed on Flag
0 0 φ_W/8
1 φ_W/4
1 _* φ_W/2
0 Operates in active (high-speed) mode
*: Don't care
1 Operates in active (medium-speed) mode
Direct Transfer on Flag
0 • When a SLEEP instruction is executed in active mode, a transition is
made to standby mode, watch mode, or sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition is
made to watch mode or subsleep mode
1 • When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in subactive mode, a direct
transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0,
and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1,
LSON = 0, and MSON = 1
Noise Elimination Sampling Frequency Select
0 Sampling rate is φ_OSC/16
1 Sampling rate is φ_OSC/4
Rev. 8.00 Mar. 09, 2010 Page 601 of 658
REJ09B0042-0800