HD64F38024HV Datasheet, PDF (29/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 1 Overview
1.2 Internal Block Diagram
Figure 1.1(1) shows a block diagram of the H8/38024 Group and H8/38024S Group.
Figure 1.1(2) shows a block diagram of the H8/38124 Group.
x₁
Sub clock
x₂
OSC
OSC₁
OSC₂
System clock
OSC
P1₃/TMIG
P1₄/IRQ₄/ADTRG
P1₆
P1₇/IRQ₃/TMIF
P3₀/UD
P3₁/TMOFL
P3₂/TMOFH
P3₃
P3₄
P3₅
P3₆/AEVH
P3₇/AEVL
P4₀/SCK₃₂
P4₁/RXD₃₂
P4₂/TXD₃₂
P4₃/IRQ₀
P5₀/WKP₀/SEG₁
P5₁/WKP₁/SEG₂
P5₂/WKP₂/SEG₃
P5₃/WKP₃/SEG₄
P5₄/WKP₄/SEG₅
P5₅/WKP₅/SEG₆
P5₆/WKP₆/SEG₇
P5₇/WKP₇/SEG₈
P6₀/SEG₉
P6₁/SEG₁₀
P6₂/SEG₁₁
P6₃/SEG₁₂
P6₄/SEG₁₃
P6₅/SEG₁₄
P6₆/SEG₁₅
P6₇/SEG₁₆
AV_CC
ROM
(8 Kbytes to 32 Kbytes)
Timer A
Timer C
Timer G
RAM
(512 bytes to 1 Kbyte)
A/D
(10 bits)
Note: If the on-chip emulator is used, pins 95,
33, 34, and 35 are reserved for the
emulator and not available to the user.
H8/300L
CPU
Asynchronous
counter
(16 bits)
10-bit PWM1
10-bit PWM2
Timer F
Serial
communication
interface
(SCI3)
V_SS
V_SS = AV_SS
V_CC
RES
TEST
IRQAEC
PA₃/COM₄
PA₂/COM₃
PA₁/COM₂
PA₀/COM₁
P9₅
P9₄
P9₃
P9₂
P9₁/PWM₂
P9₀/PWM₁
P8₇/SEG₃₂
P8₆/SEG₃₁
P8₅/SEG₃₀
P8₄/SEG₂₉
P8₃/SEG₂₈
P8₂/SEG₂₇
P8₁/SEG₂₆
P8₀/SEG₂₅
P7₇/SEG₂₄
P7₆/SEG₂₃
P7₅/SEG₂₂
P7₄/SEG₂₁
P7₃/SEG₂₀
P7₂/SEG₁₉
P7₁/SEG₁₈
P7₀/SEG₁₇
V₁
V₂
WDT
V₃
LCD
controller
PB₇/AN₇
PB₆/AN₆
PB₅/AN₅
PB₄/AN₄
PB₃/AN₃/IRQ₁/TMIC
PB₂/AN₂
PB₁/AN₁
PB₀/AN₀
Large-current (25 mA/pin) high-voltage open-drain pin (7 V)
Large-current (10 mA/pin) (H8/38024S Group only)
Large-current (10 mA/pin) high-voltage open-drain pin (7 V)
Large-current (10 mA/pin) (H8/38024S Group only)
High-voltage (7 V) input pin (Except for H8/38024S Group)
Figure 1.1(1) Block Diagram (H8/38024 Group, H8/38024R Group, and H8/38024S Group)
Rev. 8.00 Mar. 09, 2010 Page 7 of 658
REJ09B0042-0800