HD64F38024HV Datasheet, PDF (397/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 10 Serial Communication Interface
• Receiving
Figure 10.13 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
Read bit OER
in SSR
[1]
Yes
OER = 1?
No
Read bit RDRF
in SSR
[2]
RDRF = 1?
Yes
Read receive
data in RDR
No
[4]
Overrun error
processing
[1] Read bit OER in the serial status register
(SSR) to determine if there is an error.
If an overrun error has occurred, execute
overrun error processing.
[2] Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data in
RDR. When the RDR data is read, bit
RDRF is cleared to 0 automatically.
[3] When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
[4] If an overrun error has occurred, read bit
OER in SSR, and after carrying out the
necessary error processing, clear bit OER
to 0. Reception cannot be resumed if bit
OER is set to 1.
[3]
Continue data
Yes
reception?
No
Clear bit RE to
0 in SCR3
Start overrun
4
error processing
End
Overrun error
processing
Clear bit OER to
0 in SSR
End of overrun
error processing
Figure 10.13 Example of Data Reception Flowchart (Synchronous Mode)
Rev. 8.00 Mar. 09, 2010 Page 375 of 658
REJ09B0042-0800