HD64F38024HV Datasheet, PDF (626/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Appendix B Internal I/O Registers
IENR2—Interrupt Enable Register 2
H'F4
System Control
Bit
7
6
5
4
3
2
1
0
IENDT IENAD ⎯ IENTG IENTFH IENTFL IENTC IENEC
Initial value
0
0
⎯
0
0
0
0
0
Read/Write
R/W R/W
W
R/W R/W R/W R/W R/W
Asynchronous Event Counter
Interrupt Enable
0 Disables asynchronous event
counter interrupt requests
1 Enables asynchronous event
counter interrupt requests
Timer C Interrupt Enable
0 Disables timer C interrupt requests
1 Enables timer C interrupt requests
Timer FL Interrupt Enable
0 Disables timer FL interrupt requests
1 Enables timer FL interrupt requests
Timer FH Interrupt Enable
0 Disables timer FH interrupt requests
1 Enables timer FH interrupt requests
Timer G Interrupt Enable
0 Disables timer G interrupt requests
1 Enables timer G interrupt requests
A/D Converter Interrupt Enable
0 Disables A/D converter interrupt requests
1 Enables A/D converter interrupt requests
Direct Transition Interrupt Enable
0 Disables direct transition interrupt requests
1 Enables direct transition interrupt requests
Rev. 8.00 Mar. 09, 2010 Page 604 of 658
REJ09B0042-0800