HD64F38024HV Datasheet, PDF (194/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 6 ROM
Write pulse application subroutine
Apply Write Pulse
WDT enable
Set PSU bit in FLMCR1
Wait 50 μs
Set P bit in FLMCR1
Wait (Wait time = programming time)
Clear P bit in FLMCR1
Wait 5 μs
Clear PSU bit in FLMCR1
Wait 5 μs
Disable WDT
End Sub
START
Set SWE bit in FLMCR1
Wait 1 μs
Store 128-byte program data in program
data area and reprogram data area
n=1
m=0
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Apply Write pulse
Set PV bit in FLMCR1
Wait 4 μs
Set block start address as
verify address
H'FF dummy write to verify address
Wait 2 μs
Read verify data
Increment address
Verify data =
No
write data?
Yes
No
n≤6?
Yes
Additional-programming data
computation
m=1
n←n+1
Reprogram data computation
128-byte
No
data verification
completed?
Yes
Clear PV bit in FLMCR1
Wait 2 μs
n ≤ 6?
No
Yes
Successively write 128-byte data from
additional-programming data area
in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse
m=0?
No
Yes
Clear SWE bit in FLMCR1
Wait 100 μs
End of programming
n ≤ 1000 ?
Yes
No
Clear SWE bit in FLMCR1
Wait 100 μs
Programming failure
Figure 6.10 Program/Program-Verify Flowchart
Rev. 8.00 Mar. 09, 2010 Page 172 of 658
REJ09B0042-0800