HD64F38024HV Datasheet, PDF (280/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 9 Timers
Bits 6 and 5—Counter Up/Down Control (TMC6, TMC5)
Selects whether TCC up/down control is performed by hardware using UD pin input, or whether
TCC functions as an up-counter or a down-counter.
Bit 6
TMC6
0
0
1
Bit 5
TMC5
0
1
*
Description
TCC is an up-counter
TCC is a down-counter
Hardware control by UD pin input
UD pin input high: Down-counter
UD pin input low: Up-counter
(initial value)
*: Don't care
Bits 4 and 3—Reserved
Bits 4 and 3 are reserved; they are always read as 1 and cannot be modified.
Bits 2 to 0—Clock Select (TMC2 to TMC0)
Bits 2 to 0 select the clock input to TCC. For external event counting, either the rising or falling
edge can be selected.
Bit 2
TMC2
Bit 1
TMC1
Bit 0
TMC0
Description
0
0
0
Internal clock: φ/8192
(initial value)
0
0
1
Internal clock: φ/2048
0
1
0
Internal clock: φ/512
0
1
1
Internal clock: φ/64
1
0
0
Internal clock: φ/16
1
0
1
Internal clock: φ/4
1
1
0
Internal clock: φW/4
1
1
1
External event (TMIC): rising or falling edge^*
Note: * The edge of the external event signal is selected by bit IEG1 in the IRQ edge select
register (IEGR). See IRQ Edge Select Register (IEGR) in section 3.3.2, Interrupt Control
Registers, for details. IRQ1 in port mode register B (PMRB) must be set to 1 before
setting 111 in bits TMC2 to TMC0.
Rev. 8.00 Mar. 09, 2010 Page 258 of 658
REJ09B0042-0800