HD64F38024HV Datasheet, PDF (365/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Bit 7
TIE
0
1
Section 10 Serial Communication Interface
Description
Transmit data empty interrupt request (TXI) disabled
Transmit data empty interrupt request (TXI) enabled
(initial value)
Bit 6—Receive Interrupt Enable (RIE)
Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive
error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR)
to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1.
There are three kinds of receive error: overrun, framing, and parity.
RXI and ERI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by
clearing bit RIE to 0.
Bit 6
RIE
0
1
Description
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) disabled
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) enabled
(initial value)
Bit 5—Transmit Enable (TE)
Bit 5 selects enabling or disabling of the start of transmit operation.
Bit 5
TE
Description
0
Transmit operation disabled^*1 (TXD32 pin is I/O port)
(initial value)
1
Transmit operation enabled^*2 (TXD32 pin is transmit data pin)
Notes: 1. Bit TDRE in SSR is fixed at 1.
2. When transmit data is written to TDR in this state, bit TDRE in SSR is cleared to 0 and
serial data transmission is started. Be sure to carry out serial mode register (SMR)
settings, and setting of bit SPC32 in SPCR, to decide the transmission format before
setting bit TE to 1.
Rev. 8.00 Mar. 09, 2010 Page 343 of 658
REJ09B0042-0800