HD64F38024HV Datasheet, PDF (300/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 9 Timers
TCF Clear Timing
TCF can be cleared by a compare match with OCRF.
Timer Overflow Flag (OVF) Set Timing
OVF is set to 1 when TCF overflows from H'FFFF to H'0000.
Compare Match Flag Set Timing
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.
The compare match signal is generated in the last state during which the values match (when TCF
is updated from the matching value to a new value). When TCF matches OCRF, the compare
match signal is not generated until the next counter clock.
Timer F Operation Modes
Timer F operation modes are shown in table 9.9.
Table 9.9 Timer F Operation Modes
Operation Mode Reset Active Sleep Watch
Sub-
active
Sub-
sleep
Module
Standby Standby
TCF
Reset Functions Functions Functions/ Functions/ Functions/ Halted Halted
Halted^* Halted^* Halted^*
OCRF
Reset Functions Held
Held
Functions Held
Held
Held
TCRF
Reset Functions Held
Held
Functions Held
Held
Held
TCSRF
Reset Functions Held
Held
Functions Held
Held
Held
Note: * When φw/4 is selected as the TCF internal clock in active mode or sleep mode, since the
system clock and internal clock are mutually asynchronous, synchronization is maintained
by a synchronization circuit. This results in a maximum count cycle error of 1/φ (s). When
the counter is operated in subactive mode, watch mode, or subsleep mode, φw/4 must be
selected as the internal clock. The counter will not operate if any other internal clock is
selected.
Rev. 8.00 Mar. 09, 2010 Page 278 of 658
REJ09B0042-0800