HD64F38024HV Datasheet, PDF (108/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 3 Exception Handling
Bits 1 and 0—IRQ₁ and IRQ₀ Interrupt Request Flags (IRRI1 and IRRI0)
Bit n
IRRIn
0
1
Description
Clearing condition:
When IRRIn = 1, it is cleared by writing 0
(initial value)
Setting condition:
When pin IRQn is designated for interrupt input and the designated signal edge is
input
(n = 1 or 0)
Interrupt Request Register 2 (IRR2)
Bit
7
6
5
4
3
2
1
0
IRRDT IRRAD ⎯ IRRTG IRRTFH IRRTFL IRRTC IRREC
Initial value
0
0
⎯
Read/Write R/(W)^* R/(W)^* W
0
0
0
0
0
R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^*
Note: * Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer G, Timer FH, Timer FL, Timer C, or asynchronous event counter
interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is
necessary to write 0 to clear each flag.
Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7
IRRDT
0
1
Description
Clearing condition:
When IRRDT = 1, it is cleared by writing 0
(initial value)
Setting condition:
When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in
SYSCR2
Rev. 8.00 Mar. 09, 2010 Page 86 of 658
REJ09B0042-0800