HD64F38024HV Datasheet, PDF (148/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 5 Power-Down Modes
Bit 3—Low Speed on Flag (LSON)
This bit chooses the system clock (φ) or subclock (φ_SUB) as the CPU operating clock when watch
mode is cleared. The resulting operation mode depends on the combination of other control bits
and interrupt input.
Bit 3
LSON
0
1
Description
The CPU operates on the system clock (φ)
The CPU operates on the subclock (φSUB)
(initial value)
Bit 2—Reserved
Bit 2 is reserved: it is always read as 1 and cannot be modified.
Bits 1 and 0—Active (Medium-Speed) Mode Clock Select (MA1, MA0)
Bits 1 and 0 choose φ_osc/128, φ_osc/64, φ_osc/32, or φ_osc/16 as the operating clock in active (medium-
speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high-
speed) mode or subactive mode.
Bit 1
MA1
0
0
1
1
Bit 0
MA0
0
1
0
1
Description
φosc/16
φosc/32
φosc/64
φosc/128
(initial value)
System Control Register 2 (SYSCR2)
Bit
7
⎯
Initial value
1
Read/Write
⎯
6
5
4
3
2
1
0
⎯
⎯ NESEL DTON MSON SA1 SA0
1
1
1
0
0
0
0
⎯
⎯
R/W
R/W
R/W
R/W
R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5—Reserved
These bits are reserved; they are always read as 1, and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 126 of 658
REJ09B0042-0800