HD64F38024HV Datasheet, PDF (578/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Appendix B Internal I/O Registers
LVDSR—Low-Voltage Detection Status Register
H'87
Note: This register is implemented on the H8/38124 Group only.
LVDC
Bit
Initial value
Read/Write
7
OVF
0^*
R/W
6
5
4
3
2
1
0
⎯
⎯
⎯ VREFSEL ⎯ LVDDF LVDUF
0
0
0
0
0
0^*
0^*
R/W R/W R/W R/W R/W R/W R/W
LVD Power Supply Voltage Rise Flag
0 [Clearing condition]
(initial v alue)
When 0 is written after reading 1
1 [Setting condition]
When the power supply voltage drops below
Vint(D) while the LVDUE bit in LVDCR is set
to 1, and it rises above Vint(U) before
dropping below Vreset1
LVD Power Supply Voltage Drop Flag
0 [Clearing condition]
When 0 is written after reading 1
(initial value)
1 [Setting condition]
When the power supply voltage drops below Vint(D)
Reference Voltage External Input Select
0 The on-chip circuit is used to generate the reference
voltage
(initial value)
1 The reference voltage is input to the Vref pin from
an external source
LVD Reference Voltage Stabilized Flag
0 [Clearing condition]
When 0 is written after reading 1
(initial value)
1 [Setting condition]
When the low-voltage detection counter (LVDCNT) overflows
Note: * These bits initialized by resets trigged by LVDR.
Rev. 8.00 Mar. 09, 2010 Page 556 of 658
REJ09B0042-0800