HD64F38024HV Datasheet, PDF (292/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 9 Timers
Timer Control/Status Register F (TCSRF)
Bit:
Initial value:
Read/Write:
7
OVFH
0
R/(W)^*
6
CMFH
0
R/(W)^*
5
OVIEH
0
R/W
4
CCLRH
0
R/W
3
OVFL
0
R/(W)^*
2
CMFL
0
R/(W)^*
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
1
OVIEL
0
R/W
0
CCLRL
0
R/W
TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting,
and compare match flag setting, and controls enabling of overflow interrupt requests.
TCSRF is initialized to H'00 upon reset.
Bit 7—Timer Overflow Flag H (OVFH)
Bit 7 is a status flag indicating that TCFH has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 7
OVFH
0
1
Description
Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
Setting condition:
Set when TCFH overflows from H’FF to H’00
(initial value)
Bit 6—Compare Match Flag H (CMFH)
Bit 6 is a status flag indicating that TCFH has matched OCRFH. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 6
CMFH
0
1
Description
Clearing condition:
After reading CMFH = 1, cleared by writing 0 to CMFH
Setting condition:
Set when the TCFH value matches the OCRFH value
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 270 of 658
REJ09B0042-0800