HD64F38024HV Datasheet, PDF (463/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
VCC
VLVDRmin
LVDRES
Vreset
VSS
PSS-reset
signal
OVF
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 14.3 Operational Timing of LVDR Circuit
LVDI (Interrupt by Low Voltage Detect) Circuit:
Figure 14.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after
a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 150
μs (t_LVDON) until the reference voltage and the low-voltage-detection power supply have stabilized,
based on overflow of LVDNT, etc., then set the LVDDE and LVDUE bits in LVDCR to 1. After
that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first
the LVDDE and LVDUE bits should all be cleared to 0 and then the LVDE bit should be cleared
to 0. The LVDE bit must not be cleared to 0 at the same timing as the LVDDE and LVDUE bits
because incorrect operation may occur.
When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the
LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time,
an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be
saved in the external EEPROM, etc, and a transition must be made to standby mode or watch
mode. Until this processing is completed, the power supply voltage must be higher than the lower
limit of the guaranteed operating voltage.
Rev. 8.00 Mar. 09, 2010 Page 441 of 658
REJ09B0042-0800