HD64F38024HV Datasheet, PDF (307/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Register Configuration
Table 9.11 shows the register configuration of timer G.
Table 9.11 Timer G Registers
Name
Timer control register G
Timer counter G
Input capture register GF
Input capture register GR
Clock stop register 1
Abbr.
R/W
TMG
R/W
TCG
—
ICRGF
R
ICRGR
R
CKSTPR1 R/W
Section 9 Timers
Initial Value
H'00
H'00
H'00
H'00
H'FF
Address
H'FFBC
—
H'FFBD
H'FFBE
H'FFFA
9.5.2 Register Descriptions
Timer Counter G (TCG)
Bit:
Initial value:
Read/Write:
7
TCG7
0
⎯
6
TCG6
0
⎯
5
TCG5
0
⎯
4
TCG4
0
⎯
3
TCG3
0
⎯
2
TCG2
0
⎯
1
TCG1
0
⎯
0
TCG0
0
⎯
TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by
bits CKS1 and CKS0 in TMG.
TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate
TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the
rising edge, falling edge, or both edges of the input capture input signal, according to the setting
made in TMG.
When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG in IRR2 is set to 1, and if
IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.
Note: * An input capture signal may be generated when TMIG is modified.
Rev. 8.00 Mar. 09, 2010 Page 285 of 658
REJ09B0042-0800