HD64F38024HV Datasheet, PDF (138/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 4 Clock Pulse Generators
OSC1
C1
Rf
OSC2
C2
Negative resistance,
addition of −R
(1) Negative Resistance Measuring Circuit
Modification
point
C1
C2
OSC1
Rf
OSC2
Modification
point
C1
C2
OSC1
Rf
OSC2
(2) Oscillator Circuit Modification Suggestion 1
Modification
point
C3
C1
C2
OSC1
Rf
OSC2
(3) Oscillator Circuit Modification Suggestion 2
(4) Oscillator Circuit Modification Suggestion 3
Figure 4.13 Negative Resistance Measurement and Circuit Modification Suggestions
4.5.1 Definition of Oscillation Stabilization Wait Time
Figure 4.14 shows the oscillation waveform (OSC2), system clock (φ), and microcomputer
operating mode when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock
oscillator.
As shown in figure 4.13, as the system clock oscillator is halted in standby mode, watch mode,
and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the
sum of the following two times (oscillation stabilization time and wait time) is required.
Rev. 8.00 Mar. 09, 2010 Page 116 of 658
REJ09B0042-0800