HD64F38024HV Datasheet, PDF (345/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 9 Timers
Bit 2—Count-up Enable L (CUEL)
Bit 2 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECL value is held.
Bit 2
CUEL
0
1
Description
ECL event clock input is disabled
ECL value is held
ECL event clock input is enabled
(initial value)
Bit 1—Counter Reset Control H (CRCH)
Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to
this bit, the counter reset is cleared and the ECH count-up function is enabled.
Bit 1
CRCH
0
1
Description
ECH is reset
ECH reset is cleared and count-up function is enabled
(initial value)
Bit 0—Counter Reset Control L (CRCL)
Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to
this bit, the counter reset is cleared and the ECL count-up function is enabled.
Bit 0
CRCL
0
1
Description
ECL is reset
ECL reset is cleared and count-up function is enabled
(initial value)
Event Counter H (ECH)
Bit
Initial Value
Read/Write
7
ECH7
0
R
6
ECH6
0
R
5
ECH5
0
R
4
ECH4
0
R
3
ECH3
0
R
2
ECH2
0
R
1
ECH1
0
R
0
ECH0
0
R
Rev. 8.00 Mar. 09, 2010 Page 323 of 658
REJ09B0042-0800