HD64F38024HV Datasheet, PDF (308/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 9 Timers
Input Capture Register GF (ICRGF)
Bit:
Initial value:
Read/Write:
7
ICRGF7
0
R
6
ICRGF6
0
R
5
ICRGF5
0
R
4
ICRGF4
0
R
3
ICRGF3
0
R
2
ICRGF2
0
R
1
ICRGF1
0
R
0
ICRGF0
0
R
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φ_SUB (when the noise canceler is not used).
ICRGF is initialized to H'00 upon reset.
Input Capture Register GR (ICRGR)
Bit:
7
ICRGR7
Initial value: 0
Read/Write: R
6
ICRGR6
0
R
5
ICRGR5
0
R
4
ICRGR4
0
R
3
ICRGR3
0
R
2
ICRGR2
0
R
1
ICRGR1
0
R
0
ICRGR0
0
R
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 0 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φ_SUB (when the noise canceler is not used).
ICRGR is initialized to H'00 upon reset.
Rev. 8.00 Mar. 09, 2010 Page 286 of 658
REJ09B0042-0800