HD64F38024HV Datasheet, PDF (622/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Appendix B Internal I/O Registers
SYSCR1—System Control Register 1
H'F0
Bit
7
6
5
4
3
2
SSBY STS2 STS1 STS0 LSON
⎯
Initial value
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W R/W
⎯
System Control
1
MA1
1
R/W
0
MA0
1
R/W
Active (medium-speed)
Mode Clock Select
00
1
10
φ_osc/16
φ_osc/32
φ_osc/64
1 φ_osc/128
Low Speed on Flag
0 The CPU operates on the system clock (φ)
1 The CPU operates on the subclock (φ_SUB)
Standby Timer Select 2 to 0
0 0 0 Wait time = 8,192 states^*1
1 Wait time = 16,384 states^*1
1 0 Wait time = 1,024 states^*1
1 Wait time = 2,048 states^*1
1 0 0 Wait time = 4,096 states^*1
1 Wait time = 2 states^*1
1 0 Wait time = 8 states^*1
1 Wait time = 16 states^*1
Wait time = 8,192 states^*2
Wait time = 16,384 states^*2
Wait time = 32,768 states^*2
Wait time = 65,536 states^*2
Wait time = 131,072 states^*2
Wait time = 2 states^*2
Wait time = 8 states^*2
Wait time = 16 states^*2
Software Standby
0 • When a SLEEP instruction is executed in active mode, a transition is
made to sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode
1 • When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode
Notes: 1. Applies to products other than the H8/38124 Group.
2. Applies to the H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 600 of 658
REJ09B0042-0800