HD64F38024HV Datasheet, PDF (341/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 9 Timers
Bit 1—Event Counter PWM Enable
Bit 1 controls enabling/disabling of event counter PWM and selection/deselection of IRQAEC.
Bit 1
ECPWME
0
1
Description
AEC PWM halted, IRQAEC selected
AEC PWM operation enabled, IRQAEC deselected
(initial value)
Bit 0—Reserved
Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Note: Do not set this bit to 1.
Event Counter Control Register (ECCR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
ACKH1 ACKH0 ACKL1 ACKL0 PWCK2 PWCK1 PWCK0 ⎯
0
0
0
0
0
0
0
0
R/W
R/W R/W
R/W R/W
R/W
R/W
R/W
ECCR performs counter input clock and IRQAEC/IECPWM control.
Bits 7 and 6—AEC Clock Select H (ACKH1, ACKH0)
Bits 7 and 6 select the clock used by ECH.
Bit 7
ACKH1
0
1
Bit 6
ACKH0
0
1
0
1
Description
AEVH pin input
φ/2
φ/4
φ/8
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 319 of 658
REJ09B0042-0800