HD64F38024HV Datasheet, PDF (115/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 3 Exception Handling
• If the interrupt request is accepted, after processing of the current instruction is completed,
both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in
figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be
executed upon return from interrupt handling.
• The I bit of CCR is set to 1, masking further interrupts.
• The vector address corresponding to the accepted interrupt is generated, and the interrupt
handling routine located at the address indicated by the contents of the vector address is
executed.
Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when
clearing bits in an interrupt request register, always do so while interrupts are masked
(I = 1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises
between the clear instruction and an interrupt request, exception processing for the
interrupt will be executed after the clear instruction has been executed.
Rev. 8.00 Mar. 09, 2010 Page 93 of 658
REJ09B0042-0800