HD64F38024HV Datasheet, PDF (353/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 9 Timers
Mode
Active (high-speed), sleep (high-speed)
Active (medium-speed), sleep (medium-speed) (φ/16)
(φ/32)
(φ/64)
fOSC = 1 MHz to 4 MHz
Watch, subactive, subsleep, standby
(φ/128)
(φw/2)
φw = 32.768 kHz or 38.4 kHz^*
(φw/4)
(φw/8)
Note: * Does not apply to H8/38124 Group.
Maximum AEVH/AEVL Pin Input
Clock Frequency
16 MHz
2 • fOSC
fOSC
1/2 • fOSC
1/4 • fOSC
1000 kHz
500 kHz
250 kHz
3. When using the clock in the 16-bit mode, set CUEH to 1 first, then set CRCH to 1 in ECCSR.
Or, set CUEH and CRCH simultaneously before inputting the clock. After that, do not change
the CUEH value while using in the 16-bit mode. Otherwise, an error counter increment may
occur. Also, to reset the counter, clear CRCH and CRCL to 0 simultaneously or clear CRCL
and CRCH to 0 sequentially, in that order.
4. When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH,
ECPWCRL, ECPWDRH, and ECPWDRL should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying these registers.
5. The event counter PWM data register and event counter PWM compare register must be set so
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 t_cyc will occur between clock halting and interrupt acceptance.
Rev. 8.00 Mar. 09, 2010 Page 331 of 658
REJ09B0042-0800