HD64F38024HV Datasheet, PDF (125/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 4 Clock Pulse Generators
Section 4 Clock Pulse Generators
4.1 Overview
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator and system clock dividers. The subclock pulse generator
consists of a subclock oscillator circuit and a subclock divider.
In the H8/38124 Group, the system clock pulse generator includes an on-chip oscillator.
4.1.1 Block Diagram
Figure 4.1 shows a block diagram of the clock pulse generators of the H8/38024, H8/38024S, and
H8/38024R Group. Figure 4.2 shows a block diagram of the clock pulse generators of the
H8/38124 Group.
OSC₁
OSC₂
X₁
X₂
System clock ^φOSC System clock
oscillator _(fOSC) divider (1/2)
System clock pulse generator
Subclock
oscillator
φ_W
Subclock
divider
(f_W) _{(1/2, 1/4, 1/8)}
φ_OSC/2
System
clock
divider
φ_W /2
φ_W /4
φ_W /8
φ_OSC/128
φ_OSC/64
φ_OSC/32
φ_OSC/16
φ
Prescaler S
(13 bits)
φ _SUB
Subclock pulse generator
Prescaler W
(5 bits)
Figure 4.1(1) Block Diagram of Clock Pulse Generators
(H8/38024 Group, H8/38024S Group, H8/38024R Group)
φ/2
to
φ/8192
φ_W
φ_W /2
φ_W /4
φ_W /8
to
φ_W /128
Rev. 8.00 Mar. 09, 2010 Page 103 of 658
REJ09B0042-0800