HD64F38024HV Datasheet, PDF (213/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 6 ROM
6.11 Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read and written to at high speed.
• Power-down operating mode
The power supply circuit of the flash memory is partly halted and can be read under low power
consumption.
• Standby mode
All flash memory circuits are halted.
Table 6.23 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from
power-down mode or standby mode, a period to stabilize the power supply circuits that were
stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to
STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the external
clock is being used.
Table 6.23 Flash Memory Operating States
LSI Operating State
Active mode
Subactive mode
Sleep mode
Subsleep mode
Standby mode
Watch mode
Flash Memory Operating State
PDWND = 0 (Initial value)
PDWND = 1
Normal operating mode
Normal operating mode
Power-down mode
Normal operating mode
Normal operating mode
Normal operating mode
Standby mode
Standby mode
Standby mode
Standby mode
Standby mode
Standby mode
Rev. 8.00 Mar. 09, 2010 Page 191 of 658
REJ09B0042-0800