HD64F38024HV Datasheet, PDF (366/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 10 Serial Communication Interface
Bit 4—Receive Enable (RE)
Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4
RE
Description
0
Receive operation disabled^*1 (RXD32 pin is I/O port)
(initial value)
1
Receive operation enabled^*2 (RXD32 pin is receive data pin)
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
cleared to 0, and retain their previous state.
2. In this state, serial data reception is started when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.
Bit 3—Reserved (MPIE)
It’s a reserved bit.
Bit 2—Transmit End Interrupt Enable (TEIE)
Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid
transmit data in TDR when MSB data is to be sent.
Bit 2
TEIE
Description
0
Transmit end interrupt request (TEI) disabled
1
Transmit end interrupt request (TEI) enabled^*
(initial value)
Note: * TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by
clearing bit TEIE to 0.
Rev. 8.00 Mar. 09, 2010 Page 344 of 658
REJ09B0042-0800