HD64F38024HV Datasheet, PDF (106/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 3 Exception Handling
Bit 1—Timer C Interrupt Enable (IENTC)
Bit 1 enables or disables timer C overflow and underflow interrupt requests.
Bit 1
IENTC
0
1
Description
Disables timer C interrupt requests
Enables timer C interrupt requests
(initial value)
Bit 0—Asynchronous Event Counter Interrupt Enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC
0
1
Description
Disables asynchronous event counter interrupt requests
Enables asynchronous event counter interrupt requests
(initial value)
For details of SCI3 interrupt control, see section 10.2.6 Serial control register 3 (SCR3).
Interrupt Request Register 1 (IRR1)
Bit
7
6
IRRTA
⎯
Initial value
0
⎯
Read/Write R/(W)^*
W
5
4
3
2
1
0
⎯
IRRI4 IRRI3 IRREC2 IRRI1 IRRI0
1
0
0
0
0
0
⎯
R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^*
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
IRQAEC, IRQ₄, IRQ₃, IRQ₁, or IRQ₀ interrupt is requested. The flags are not cleared
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Rev. 8.00 Mar. 09, 2010 Page 84 of 658
REJ09B0042-0800