HD64F38024HV Datasheet, PDF (155/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 5 Power-Down Modes
5.3.5 Notes on External Input Signal Changes before/after Standby Mode
1. When external input signal changes before/after standby mode or watch mode
When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and
low-level widths of the signal must be at least two cycles of system clock φ or subclock φ_SUB
(referred to together in this section as the internal clock). As the internal clock stops in
standby mode and watch mode, the width of external input signals requires careful attention
when a transition is made via these operating modes. Ensure that external input signals
conform to the conditions stated in 3, Recommended timing of external input signals, below
2. When external input signals cannot be captured because internal clock stops
The case of falling edge capture is illustrated in figure 5.3.
As shown in the case marked "Capture not possible," when an external input signal falls
immediately after a transition to active (high-speed or medium-speed) mode or subactive
mode, after oscillation is started by an interrupt via a different signal, the external input signal
cannot be captured if the high-level width at that point is less than 2 t_cyc or 2 t_subcyc.
3. Recommended timing of external input signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of
at least 2 t_cyc or 2 t_subcyc are necessary before a transition is made to standby mode or watch
mode, as shown in “Capture possible: case 1” in figure 5.3.
External input signal capture is also possible with the timing shown in “Capture possible: case
2” and “Capture possible: case 3” in figure 5.3, in which a 2 t_cyc or 2 t_subcyc level width is
secured.
Rev. 8.00 Mar. 09, 2010 Page 133 of 658
REJ09B0042-0800