HD64F38024HV Datasheet, PDF (117/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 3 Exception Handling
SP − 4
SP − 3
SP − 2
SP − 1
SP (R7)
Stack area
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
CCR
CCR^*
PC_H
PC_L
Even address
Prior to start of interrupt
exception handling
[Legend]
PC and CCR
saved to stack
PC_H: Upper 8 bits of program counter (PC)
PC_L: Lower 8 bits of program counter (PC)
CCR: Condition code register
SP: Stack pointer
After completion of interrupt
exception handling
Notes: 1. PC shows the address of the first instruction to be executed upon
return from the interrupt handling routine.
2. Register contents must always be saved and restored by word access,
starting from an even-numbered address.
* Ignored on return.
Figure 3.4 Stack State after Completion of Interrupt Exception Handling
Figure 3.5 shows a typical interrupt sequence.
Rev. 8.00 Mar. 09, 2010 Page 95 of 658
REJ09B0042-0800