HD64F38024HV Datasheet, PDF (293/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 9 Timers
Bit 5—Timer Overflow Interrupt Enable H (OVIEH)
Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows.
Bit 5
OVIEH
0
1
Description
TCFH overflow interrupt request is disabled
TCFH overflow interrupt request is enabled
(initial value)
Bit 4—Counter Clear H (CCLRH)
In 16-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match.
In 8-bit mode, bit 4 selects whether TCFH is cleared when TCFH and OCRFH match.
Bit 4
CCLRH
0
1
Description
16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
(initial value)
Bit 3—Timer Overflow Flag L (OVFL)
Bit 3 is a status flag indicating that TCFL has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 3
OVFL
0
1
Description
Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
Setting condition:
Set when TCFL overflows from H’FF to H’00
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 271 of 658
REJ09B0042-0800