HD64F38024HV Datasheet, PDF (127/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 4 Clock Pulse Generators
4.1.3 Register Descriptions
Table 4.1 lists the registers that control the clock pulse generators. The registers listed in table 4.1
are only implemented in the H8/38124 Group.
Table 4.1 Clock Pulse Generator Control Registers
Name
Clock pulse generator control
register
Abbreviation R/W
OSCCR
R/W
Initial Value
—
Address
H'FFF5
Clock Pulse Generator Control Register (OSCCR)
Bit
7
6
SUBSTP —
Initial value
0
0
Read/Write R/W
R
5
4
—
—
0
0
R/W
R/W
3
2
1
0
— IRQAECF OSCF
—
0
—
—
0
R/W
R
R
R/W
OSCCR is an 8-bit read/write register that contains the flag indicating the selection of system
clock oscillator or on-chip oscillator, indicates the input level of the IRQAEC pin during resets,
and controls whether the subclock oscillator operates or not.
Bit 7—Subclock Oscillator Stop Control (SUBSTP)
Bit 7 controls whether the subclock oscillator operates or not. It can be set to 1 only in the active
mode (high-speed/medium-speed). Setting bit 7 to 1 in the subactive mode will cause the LSI to
stop operating.
Bit 7
SUBSTP
0
1
Description
Subclock oscillator operates
Subclock oscillator stopped
(initial value)
Bit 6—Reserved
This bit is reserved. It is always read as 0 and cannot be written to.
Bits 5 to 3—Reserved
These bits are read/write enabled reserved bits.
Rev. 8.00 Mar. 09, 2010 Page 105 of 658
REJ09B0042-0800