UPD784938 Datasheet, PDF (93/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 3 CPU ARCHITECTURE
Figure 3-13. General-Purpose Register Addresses
FEFFH^Note
FE80H^Note
RBNK0
RBNK1
RBNK2
RBNK3
RBNK4
RBNK5
RBNK6
RBNK7
8-bit processing
H (R15) (FH) L (R14) (EH)
D (R13) (DH) E (R12) (CH)
R11(BH)
R10 (AH)
R9 (9H)
R8 (8H)
R7 (7H)
R6 (6H)
R5 (5H)
R4 (4H)
B (R3) (3H)
C (R2) (2H)
A (R1) (1H)
X (R0) (0H)
7
07
0
16-bit processing
HL (RP7) (EH)
DE (RP6) (CH)
UP (RP5) (AH)
VP (RP4) (8H)
RP3 (6H)
RP2 (4H)
BC (RP1) (2H)
AX (RP0) (0H)
15
0
Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H should
be added to the address values shown above.
Caution R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers respectively by setting
the RSS bit of the PSW to 1, but this function should only be used when using a 78K/III Series program.
Remark When the register bank is changed, and it is necessary to return to the original register bank, an SEL RBn
instruction should be executed after saving the PSW to the stack with a PUSH PSW instruction. When returning
to the original register bank, if the stack location does not change the POP PSW instruction should be used.
When the register bank is changed by a vectored interrupt service program, etc., the PSW is automatically saved
to the stack when an interrupt is acknowledged and restored by an RETI or RETB instruction, so that, if only one
register bank is used in the interrupt service routine, only an SEL RBn instruction needs be executed, and
execution of a PUSH PSW and POP PSW instruction is not necessary.
Example When register bank 2 is specified
PUSH PSW
SEL RB2 _


 Operations in register bank 2


POP PSW ^
Operations in original register bank
Preliminary User’s Manual U13987EJ1V0UM00
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