UPD784938 Datasheet, PDF (248/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 9 TIMER/EVENT COUNTER 0
If a value equal to or less than the TM0 value is written to CR00 before the compare register (CR00) and timer counter 0
(TM0) match, the duty of the PPG cycle will be 100%. CR00 rewriting should be performed by the interrupt due to a match
between TM0 and CR00.
Figure 9-26. Example of 100% Duty with PPG Output
CR01
CR01
CR01
CR01
TM0
count value
0H
n1
n1
n3
n2
n2
n2
CR00
n1
n2
TO0
When value n2 which is smaller than the TM0 value n3
is written to CR00 here, the duty of this period will be 100%.
Remark ALV0 = 0
Caution If the PPG cycle is extremely short as compared with the time required to acknowledge an interrupt, the
value of CR00 cannot be rewritten by interrupt processing that is performed on coincidence between TM0
and CR00. Use another method (for example, to poll the interrupt request flags by software with all the
interrupts masked).
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Preliminary User’s Manual U13987EJ1V0UM00