UPD784938 Datasheet, PDF (523/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 22 EDGE DETECTION FUNCTION
22.4 Pin Edge Detection for Pins P22 to P24
Edge detection for pins P22 to P24 is performed after digital noise elimination by means of clock sampling. Unlike the
P21 pin, fCLK is used as the sampling clock.
In digital noise elimination, input is sampled using the fCLK clock, and if the input level is not the same at least three times
in succession (if it is the same only two or fewer times in succession), it is eliminated as noise. Therefore, the level must
be maintained for at least 3 fCLK clock cycles (0.24 µs: fCLK = 12.58 MHz) in order to be recognized as a valid edge.
Figure 22-6. Edge Detection for Pins P22 to P24
P22 to P24 input
fCLK
P22 to P24 input signal
after noise elimination
Rising edge
Falling edge
Digital noise elimination
with fCLK clock
Cautions 1. Since digital noise elimination is performed with the fCLK clock, there is a delay of 2 to 3 fCLK clocks
between input of an edge to the pin and the point at which the edge is actually detected.
2. If the input pulse width is 2 to 3 fCLK clocks, it is uncertain whether a valid edge will be detected.
Therefore, to ensure reliable operation, the level should be held for at least 3 clocks.
3. If noise input to a pin is synchronized with the fCLK clock in the µPD784938, it may not be recognized
as noise. If there is a possibility of such noise being input, noise should be eliminated by adding
a filter to the input pins.
Preliminary User’s Manual U13987EJ1V0UM00
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