UPD784938 Datasheet, PDF (324/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 11 TIMER/EVENT COUNTER 2
11.6 One-Shot Timer Function
Timer/event counter 2 has an operation mode in which it stops automatically when a full count value is reached (FFH/
FFFFH) as a result of counting by timer counter 2 (TM2/TM2W).
Figure 11-14. One-Shot Timer Operation
FFH or FFFFH
TM2/TM2W
count value
0H
INTC21
interrupt request
Count start
CE2 ← 1
CR21/CR21W value
Clear
OVF2 ← 0
OVF2
As shown in Figure 11-14, the respective one-shot interrupt is generated when the value (0H to FFH/FFFFH) set
beforehand in the CR20, CR21/CR21W, or CR21W and TM2/TM2W value match.
The one-shot timer operation mode is specified by setting (to 1) bit 5 (CMD2) of timer control register 1 (TMC1) by
software.
The TM2/TM2W count operation is controlled by the CE2 bit of the TMC1 as with the basic operation.
When the CE2 bit is set (to 1) by software, the contents of TM2/TM2W are set to 0H and the count-up operation is started
on the initial count clock.
When the contents of TM2/TM2W reach FFH/FFFFH (full count) as a result of the count-up operation, bit 6 (OVF2) of
the TMC1 are set (to 1), and TM2/TM2W stops with the count at FFH/FFFFH.
The one-shot timer operation is started again from the count-stopped state by clearing (to 0) the OVF2 bit by software.
When the OVF2 bit is cleared (to 0), the contents of TM2/TM2W become 0H and the count-up operation is restarted on
the next count clock.
If the CE2 bit is cleared (to 0) by software during a TM2/TM2W count operation, the contents of TM2/TM2W are set to
0H immediately and the stopped state is entered. The TM2/TM2W count operation is not affected if the CE2 bit is set (to
1) by software again when it is already set (to 1).
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Preliminary User’s Manual U13987EJ1V0UM00