UPD784938 Datasheet, PDF (34/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

LIST OF FIGURES (12/12)
Figure No.
Title
Page
24-16
24-17
24-18
24-19
24-20
24-21
Refresh Area Specification Register (RFA) Format ................................................................................... 630
Pulse Refresh Operation in Internal Memory Access ................................................................................ 631
Refresh Pulse Output Operation ................................................................................................................. 632
Timing for Return from Self-Refresh Operation .......................................................................................... 633
Hold Mode Register (HLDM) Format .......................................................................................................... 634
Hold Mode Timing ........................................................................................................................................ 635
25-1
25-2
25-3
25-4
25-5
25-6
25-7
Standby Mode Transition Diagram .............................................................................................................. 637
Standby Function Block Diagram ................................................................................................................ 638
Standby Control Register (STBC) Format .................................................................................................. 640
Oscillation Stabilization Time Specification Register (OSTS) Format ....................................................... 641
STOP Mode Release by NMI Input ............................................................................................................. 648
STOP Mode Release by INTP4/INTP5 Input ............................................................................................. 649
Example of Address/Data Bus Processing ................................................................................................. 654
26-1
26-2
26-3
Reset Signal Acknowledgment .................................................................................................................... 657
Power-On Reset Operation ......................................................................................................................... 658
Reset Input Timing ....................................................................................................................................... 661
27-1
27-2
27-3
27-4
ROM Correction Block Diagram .................................................................................................................. 665
Memory Mapping Example (µPD784938) ................................................................................................... 666
ROM Correction Address Register (CORAH, CORAL) Format ................................................................. 667
ROM Correction Control Register (CORC) Format .................................................................................... 668
28-1
28-2
28-3
28-4
Internal Memory Size Switching Register (IMS) Format ............................................................................ 672
Communication Mode Selection Format ..................................................................................................... 673
Flashpro II and Flashpro III Connection in 3-Wire Serial I/O Mode .......................................................... 675
Flashpro II and Flashpro III Connection in UART Mode ............................................................................ 675
A-1 Development Tool Configuration ................................................................................................................. 710
A-2 Package Drawing of EV-9200GF-100 (reference) (unit: mm) .................................................................... 718
A-3 Recommended Board Mounting Pattern of EV-9200GF-100 (reference) (unit: mm) ............................... 719
34
Preliminary User’s Manual U13987EJ1V0UM00