UPD784938 Datasheet, PDF (498/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 20 IEBus CONTROLLER
(10) Slave status register (SSR)
This register indicates the communication status of the slave unit. After receiving a slave status transmission request
from the master, the CPU reads this register, and writes a slave status to the data register (DR) to transmit the slave
status. At this time, the telegraph length is automatically set to “01H” that setting of telegraph length register (DLR)
is not required (because it is preset by hardware).
Figure 20-25. Slave Status Register (SSR) Format
7
6
5
4
3
2
1
0 Address After reset R/W
SSR 0
1
0 STATSLV 0 STATLOCK STATRX STATTX 0FFBDH 41H
R
STATTX
DR Transmit Status
0 Transmission data not stored in DR
1 Transmission data stored in DR
STATRX
DR Receive Status
0 Receiving data not stored in DR
1 Receiving data stored in DR
STATLOCK
Lock Status Flag
0 Unlock status
1 Lock status
STATSLV
Slave Transmission Enable Flag
0 Slave transmission stops
1 Slave transmission enabled
• Slave transmission status flag (STATSLV) ... Bit 4
Reflects the content of the slave transmission enable flag.
• Lock status flag (STATLOCK) ... Bit 2
Reflects the content of the lock status flag.
• DR receive status (STATRX) ... Bit 1
The flag that indicates the receive status of the DR.
• DR transmit status (STATTX) ... Bit 0
The flag that indicates the transmit status of the DR.
Bits 6 and 7 indicate the highest mode supported by the unit, and are fixed to “01H” (mode 1).
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Preliminary User’s Manual U13987EJ1V0UM00