UPD784938 Datasheet, PDF (494/733 Pages) NEC – 16-Bit Single-Chip Microcontrollers

CHAPTER 20 IEBus CONTROLLER
(9) Interrupt status register (ISR)
This status register indicates the status when an interrupt of the IEBus is issued. User must read this register and
perform the subsequent processing each time an interrupt has been generated.
Clear the contents of the following communication error flag (IEERR), start interrupt flag (START), and status
transmission flag (STATUS) through software manipulation in vector interrupt processing. Also be sure to check and
clear the contents of the communication end flag (ENDTRANS) and frame end flag (ENDFRAM) through software
manipulation.
Figure 20-24. Interrupt Status Register (ISR) Format
7
6
5
4
3
2
1
ISR 0 IEERR START STATUS ENDTRNS ENDFRAM 0
0 Address After reset R/W
0 0FFBCH 00H R/W
ENDFRAM
Frame End Flag
0 Frame does not end
1 Frame ends
ENDTRNS
Communication End Flag
0 Communication does not end
1 Communication ends
STATUS
Status Transmission Flag
0 No status transmission request
1 Status transmission request
START
Start Interrupt Flag
0 Interrupt after ACK period of slave address
field
1 Interrupt during ACK period of slave
address field
IEERR
Communication Error Flag
0 No communication error
1 Communication error occurs
Remark Reset of IEER, STARTF, and STATUSF flags is performed by writing a byte in to the interrupt status register
(ISR).
494
Preliminary User’s Manual U13987EJ1V0UM00